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K4E661612C,K4E641612C
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
* Part Identification - K4E661612C-TC/L(3.3V, 8K Ref.) - K4E641612C-TC/L(3.3V, 4K Ref.) * Extended Data Out Mode operation * 2 CAS Byte/Word Read/Write operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Fast parallel test mode capability * Self-refresh capability (L-ver only) * Active Power Dissipation Unit : mW Speed -45 -50 -60 8K 324 288 252 4K 468 432 396 * LVTTL(3.3V) compatible inputs and outputs * Early Write or output enable controlled write * JEDEC Standard pinout * Available in Plastic TSOP(II) packages * +3.3V0.3V power supply
* Refresh Cycles Part NO. K4E661612C* K4E641612C Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS UCAS LCAS W Control Clocks Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) * Performance Range Speed -45 -50 -60
Refresh Timer Refresh Control Refresh Counter
Row Decoder
DQ0 to DQ7
Memory Array 4,194,304 x 16 Cells
OE DQ8 to DQ15
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
tRC
74ns 84ns 104ns
tHPC
17ns 20ns 25ns
A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
K4E661612C,K4E641612C
CMOS DRAM
PIN CONFIGURATION (Top Views)
* K4E661612C-T * K4E641612C-T VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product
Pin Name A0 - A12 A0 - A11 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C
Pin function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
K4E661612C,K4E641612C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Address Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50
CMOS DRAM
Units V V C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3 *2 Typ 3.3 0 Max 3.6 0 Vcc+0.3*1 0.8 Units V V V V
*1 : Vcc+1.3V at pulse width15ns which is measured at VCC *2 : -1.3 at pulse width15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
K4E661612C,K4E641612C
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed K4E661612C ICC1 Dont care Normal L Dont care -45 -50 -60 Dont care -45 -50 -60 -45 -50 -60 Dont care -45 -50 -60 Dont care Dont care 90 80 70 1 1 90 80 70 100 90 80 0.5 200 130 120 110 350 350 Max K4E641612C 130 120 110 1 1 130 120 110 100 90 80 0.5 200 130 120 110 350 350
CMOS DRAM
Units mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA
ICC2
ICC3
ICC4
Dont care Normal L Dont care L L
ICC5
ICC6 ICC7 ICCS
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V W, OE=VIH, Address=Dont care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
K4E661612C,K4E641612C
CAPACITANCE (TA=25C, VCC=3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0CTA70C, See note 2)
Test condition : VCC=3.3V0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Symbol Min -45 Max Min 84 113 45 12 23 3 3 3 1 25 45 8 35 7 11 9 5 0 7 0 7 23 0 0 0 7 6 8 7 0 5K 33 22 10K 50 13 3 3 3 1 30 50 8 38 8 11 9 5 0 7 0 7 25 0 0 0 7 7 8 7 0 10K 37 25 10K 50 13 50 13 25 3 3 3 1 40 60 10 40 10 14 12 5 0 10 0 10 30 0 0 0 10 10 10 10 0 10K 45 30 10K 50 13 -50 Max Min 104 138 60 15 30 -60 Max Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16 9,19 8 8 13 13 4 10 3,4,10 3,4,5 3,10 3 6,20 3 2 Note
tRC tRWC tRAC tCAC tAA tCLZ tCEZ tOLZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS
74 101
K4E661612C,K4E641612C
AC CHARACTERISTICS (Continued)
Parameter Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay CAS precharge to W delay time Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -45 Max Min 7 64 128 0 24 57 35 5 10 5 24 17 47 6.5 45 24 12 8 36 3 5 10 10 10 10 4 3 3 8 5 5 5 5 100 74 -50 13 13 11 10 41 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 90 -50 13 13 13 200K 20 47 7 50 30 13 13 52 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 110 -50 200K 0 27 64 39 5 10 5 28 25 56 10 60 35 64 128 0 32 77 47 5 10 5 -50 Max Min 10 -60
CMOS DRAM
Units Max ns 64 128 ms ms ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns ns 13 ns ns ns ns ns ns ns 13 13 ns ns ns ns ns ns ns us ns ns
Note 9,19
tDH tREF tREF tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tCPWD tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS
7
7 7,15 7 7 17 18
3 21 21 14
3
6
11 11
6,20 6
22,23,24 22,23,24 22,23,24
K4E661612C,K4E641612C
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Hyper Page cycle time Hyper Page read-modify-write cycle time RAS pulse width (Hyper page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 89 121 50 17 28 50 12 18 39 28 29 62 40 22 52 50 200K 29 17 13 13 18 18 10K 10K 55 13 18 43 30 35 72 47 25 53 55 200K 33 18 20 20 55 18 30 10K 10K 65 15 20 50 35 39 84 54 30 61 65 -50 Max Min 109 145 65 20 35 -60
CMOS DRAM
( Note 11 )
Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 3 7 7 7 21 21 3,4,10,12 3,4,5,12 3,10,12 Note
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH
79 110
10K 10K
K4E661612C,K4E641612C
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCStWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifiecations are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tASC, tCAH are referenced to the earlier CAS falling edge. 14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
K4E64(6)1612C Truth Table
RAS H L L L L L L L L LCAS X H L H L L H L L UCAS X H H L L H L L L W X X H H H L L L H OE X X L L L H H H H DQ0 - DQ7 Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write -
K4E661612C,K4E641612C
16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to earlier CAS falling before RAS transition low. 18. tCHR is referenced to the later CAS rising high after RAS transition low.
CMOS DRAM
RAS
LCAS
UCAS
tCSR
tCHR
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle. LCAS UCAS
tDS
DQ0 ~ DQ15 Din
tDH
20. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. 21. tASC6ns, Assume tT=2.0ns, if tASC6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC". 22. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 23. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 24. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
K4E661612C,K4E641612C
WORD READ CYCLE
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCSH tRCD tRSH tCAS tCRP tCRP
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH
tAA tOLZ
OE VIH VIL -
tOEA tCAC tCLZ tCEZ tOEZ
DATA-OUT
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL -
tRAC OPEN
tCAC tRAC OPEN tCLZ tOEZ
DATA-OUT
tCEZ
Dont care Undefined
K4E661612C,K4E641612C
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tCSH tRCD tRAD tRSH tCAS
tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tCEZ tAA tOEZ tOEA tCAC tCLZ
DATA-OUT
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL -
tRAC OPEN
tOLZ OPEN
Dont care Undefined
K4E661612C,K4E641612C
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tRPC tRAD tRAL tCRP
tCRP
LCAS VIH VIL -
tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tCEZ tAA tOEZ tOEA tOLZ
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL -
OPEN tCAC tRAC OPEN tCLZ
DATA-OUT
Dont care Undefined
K4E661612C,K4E641612C
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCSH tRCD tRSH tCAS
tCRP
tCRP
LCAS VIH VIL -
tCRP
tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCRP
LCAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
K4E661612C,K4E641612C
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tCRP
LCAS VIH VIL -
tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCSH tRCD tRSH tCAS
tCRP
tCRP
LCAS VIH VIL -
tCRP
tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
K4E661612C,K4E641612C
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS
tCRP
tCRP
LCAS VIH VIL -
tCRP
tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
W
VIH VIL -
tCWL tRWL tWP
OE
VIH VIL -
tOED
tOEH
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
WORD READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRCD
tRSH tCAS
tCRP
LCAS VIH VIL -
tRCD tRAD
tRSH tCAS tCSH
tASR
A VIH VIL -
tRAH
tASC
tCAH
ROW ADDR.
COLUMN ADDRESS
tAWD tCWD
W VIH VIL VIH VIL -
tRWL tCWL tWP
tRWD tOEA tOLZ tCLZ tCAC tAA tOED tOEZ
VALID DATA-OUT
OE
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC
tDS
tDH
VALID DATA-IN
tOLZ tCLZ tCAC tAA
DQ8 ~ DQ15 VI/OH VI/OL -
tRAC
tOED tOEZ
VALID DATA-OUT
tDS
tDH
VALID DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
LOWER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tRCD
tRSH tCAS
tRAD tCSH tASR tRAH tASC tCAH
A
VIH VIL -
ROW ADDR.
COLUMN ADDRESS
tAWD tCWD
W VIH VIL VIH VIL -
tRWL tCWL tWP
tRWD tOEA
OE
tOLZ tCLZ tCAC tAA
DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VOH VOL -
tRAC
tOED tOEZ
VALID DATA-OUT
tDS
tDH
VALID DATA-IN
OPEN
Dont care Undefined
K4E661612C,K4E641612C
UPPER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRCD
tRSH tCAS
tCRP
LCAS VIH VIL -
tRPC
tRAD tCSH tASR tRAH tASC tCAH
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL VIH VIL -
tRWL tCWL tWP
tRWD tOEA
OE
DQ0 ~ DQ7 VOH VOL -
OPEN tOLZ tCLZ tCAC tAA tRAC
DQ8 ~ DQ15 VI/OH VI/OL -
tOED tOEZ
VALID DATA-OUT
tDS
tDH
VALID DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE WORD READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP
tCSH tCRP
UCAS VIH VIL -
tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS
tRCD
tCAS
tCRP
LCAS VIH VIL -
tRCD tRAD tRAH tASC
tCP tCAS tCAS
tCP tCAS
tCP tCAS
tREZ
tASR
A VIH VIL -
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tAA tCPA tCAC tOCH tOEA tOEA tCAC tOEP tDOH
VALID DATA-OUT
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL -
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOLZ tCLZ tCAC
DQ8 ~ DQ15 VOH VOL -
tOEP tDOH
VALID DATA-OUT
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOLZ tCLZ
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE LOWER BYTE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCRP
UCAS VIH VIL -
tRPC tCSH tHPC tRCD tCP tCAS tCAS tCP tCAS tHPC tCP tCAS tRHCP tHPC tREZ
LCAS
VIH VIL -
tASR
A VIH VIL -
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH tASC
COLUMN ADDR
tCAH
COLUMN ADDRESS
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tAA
OE VIH VIL -
tAA tCPA tCAC tOCH tOEA
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
tOEA tCAC tOEP tDOH
VALID DATA-OUT
DQ0 ~ DQ7 VOH VOL -
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
DQ8 ~ DQ15 VOH VOL -
tOLZ tCLZ OPEN
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE UPPER BYTE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCSH tCRP
UCAS VIH VIL -
tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRPC
tRCD tCAS
tCRP
LCAS VIH VIL -
tRPC
tASR
A VIH VIL -
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR.
tASC
tCAH
tREZ
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tAA tCPA tCAC tOCH tOEA tOEA
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL -
OPEN tCAC tOEP tDOH
VALID DATA-OUT
DQ8 ~ DQ15 VOH VOL -
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOLZ tCLZ
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
UCAS VIH VIL -
tHPC tRCD tCAS tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS
o
tHPC tCP tCAS
o
tRSH tCP tCAS tCRP
tCRP
LCAS VIH VIL -
tHPC tCP
tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tRPC tCRP
UCAS VIH VIL -
tCRP
LCAS VIH VIL -
tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS
o
tHPC tCP
tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
UCAS VIH VIL -
tHPC tRCD tCAS tCP tCAS
o
tHPC tCP
tRSH tCAS tRPC
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tCSH tASC
tRAL tCAH tASC tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
o o
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tHPRWC tRSH
tCSH tCRP
tRCD tCAS
tCP tCAS tCP tCAS tCAS
tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRCD
tCRP
tRAD tRAH tASR
A VIH VIL ROW ADDR
tASC
COL. ADDR
tCAH tASC
COL. ADDR
tRAL tCAH
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDS tDH
tRCS tCWD tAWD tCPWD tOEA
tRWL tCWL tWP
OE
VIH VIL -
tOED tCAC tAA tOEZ tDS tDH
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tOED tCAC tAA
DQ8 ~ DQ15 VI/OH VI/OL -
tDH tOEZ tDS
tCAC tAA tOEZ
tOED tDH tDS
tRAC tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tHPRWC tRPC
tCSH tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRCD tCAS tRAD tRAH
tCP
tRSH tCAS
tCRP
tASR
A VIH VIL ROW ADDR
tASC
COL. ADDR
tCAH tASC
COL. ADDR
tRAL tCAH
tRCS
W VIH VIL -
tCWL tWP
tRCS
tRWL tCWL tWP
tCWD tAWD tRWD tOEA tCAC tAA tOEZ tOED tDH tDS tCAC
tCWD tAWD tCPWD tOEA tOED tAA tOEZ tDH tDS
OE
VIH VIL -
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC
tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
DQ8 ~ DQ15 VI/OH VI/OL -
OPEN
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tHPRWC tRSH tCAS tRPC
tCSH tCRP
tRCD tCAS
tCP
tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRAD tRAH tASR
A VIH VIL ROW ADDR
tASC
COL. ADDR
tCAH
tASC
COL. ADDR
tCAH
tRAL
tRCS
W VIH VIL -
tCWL tWP
tRCS
tRWL tCWL tWP tCWD tAWD tCPWD
tCWD tAWD tRWD tOEA
OE
VIH VIL -
tOEA
DQ0 ~ DQ7 VI/OH VI/OL -
OPEN tOLZ tOED tCAC tAA tOEZ tDH tDS tCAC tAA tOEZ tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tOLZ tOED tDH tDS
DQ8 ~ DQ15 VI/OH VI/OL -
tRAC tCLZ
Dont care Undefined
K4E661612C,K4E641612C
HYPER PAGE READ AND WRITE MIXED CYCLE
CMOS DRAM
tRASP
RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA)
tRP
tHPC tCP
VIH UCAS VIL -
tHPC tCP tCP tCAS tHPC tCP tCAS tCAH tCP
tRHCP tHPC tCAS tHPC tCAS
tRCD
tCAS tCP
tCAS tHPC
LCAS
VIH VIL -
tRAD tASR tRAH tASC
tCAS
tCAS
tCAH
tASC
COLUMN ADDRESS
tCAH
tASC
tASC
tCAH
COL. ADDR
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
COL. ADDR
tRAL tRCS
W VIH VIL -
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE tCLZ tCPA
OE VIH VIL -
tWED
DQ0 ~ DQ7 VI/OH VI/OL -
tOEA tCAC tAA tRAC tOEA tCAC tAA tRAC
tWEZ
tWEZ
VALID
DATA-OUT
tDH tDS
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
VALID DATA-OUT
tWEZ
tWEZ
VALID
DATA-OUT
tDH tDS
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
DQ8 ~ DQ15 VI/OH VI/OL -
VALID DATA-OUT
Dont care Undefined
K4E661612C,K4E641612C
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Dont care DOUT = OPEN tRC
RAS VIH VIL -
CMOS DRAM
tRP
tRAS tCRP tRPC
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tASR
A VIH VIL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Dont care tRP
RAS VIH VIL -
tRC tRAS tRPC tCSR tCHR
tRP
tRPC tCP
UCAS
VIH VIL -
tCP
LCAS VIH VIL -
tCSR
tCHR
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL VIH VIL -
tCEZ OPEN
OPEN tWRP tWRH
W
Dont care Undefined
K4E661612C,K4E641612C
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
UCAS VIH VIL -
tRCD
tRSH
tCHR
tCRP
LCAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tRCS
W VIH VIL -
tWRH
tRAL tAA
OE
VIH VIL -
tOEA tCEZ tREZ tWEZ tOLZ tOEZ
DATA-OUT
tCAC tCLZ
DQ0 ~ DQ7 VOH VOL -
tRAC OPEN
DQ8 ~ DQ15 VOH VOL -
OPEN
DATA-IN DATA-OUT
Dont care Undefined
* In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
K4E661612C,K4E641612C
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
UCAS VIH VIL -
tRCD
tRSH
tCHR
tCRP
LCAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tWRH tWCS
W VIH VIL -
tWRP tWCH tWP
OE
VIH VIL -
tDS
DQ0 ~ DQ7 VIH VIL -
tDH
DATA-IN
tDS
DQ8 ~ DQ15 VIH VIL -
tDH
DATA-IN
Dont care Undefined
K4E661612C,K4E641612C
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Dont care tRP
RAS VIH VIL -
CMOS DRAM
tRASS
tRPS
tRPC tCP
UCAS VIH VIL -
tRPC tCSR tCHS
tCP
LCAS VIH VIL -
tCSR
tCHS
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL VIH VIL -
tCEZ OPEN
OPEN tWRP tWRH
W
TEST MODE IN CYCLE
NOTE : OE , A = Dont care tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tCSR tCHR
tRPC
UCAS
VIH VIL -
tCP
LCAS VIH VIL -
tCSR
tCHR
W
VIL VIH -
tWTS
tWTH
DQ0 ~ DQ15 VOH VOL -
tCEZ OPEN
Dont care Undefined
K4E661612C,K4E641612C
PACKAGE DIMENSION
50 TSOP(II) 400mil
CMOS DRAM
Units : Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25)
0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45)

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